La-e791p Rev 2.0 Schematic Diagram
La-e791p Rev 2.0 (also known as CSL50/CSL52) is a specialized motherboard schematic used primarily in
The schematic covers a system architecture typically built around the Intel Skylake-U (6th Gen) or Kaby Lake-U (7th/8th Gen) processors. La-e791p Rev 2.0 Schematic Diagram
Disclaimer: This article is for educational purposes. Schematics are copyrighted by Dell/Compal. Ensure you own the physical motherboard before downloading proprietary repair data. La-e791p Rev 2
LA-E791P Rev 2.0 (code-named ) is a professional-grade motherboard schematic designed by Compal Electronics for mid-range HP laptops . It is primarily found in the series and Visual Inspection: Open the schematic to Page 2
- Visual Inspection: Open the schematic to Page 2. Check all public points (PJP400 - DC Jack). Look for burnt MOSFETs PQ5001/PQ5002.
- Measure DC-in: Use the schematic to find the main fuse (PF5001). Is 19V passing? If not, short.
- Check REGN: Look at U5000 (BQ24780S). The schematic says Pin 24 (REGN) should output 6.0V. If 0V, IC is dead.
- Check ACOK: Trace the ACOK line. It should go high (3.3V). If low, the schematic leads you to the pull-up resistor (RP5003).
- Finally, LDO: Check +3.3V_ALW and +5V_ALW. If absent, the schematic directs you to check the enable signal from the SIO (IT8987E).
- Page 2-3: DC-in and Charging – Includes protection circuitry (back-to-back MOSFETs), AC detect, and SMBus for battery communication.
- Page 5-6: Always-on LDOs – +3.3V_ALW and +5V_ALW, critical for EC and PCH deep sleep well.
- Page 8-10: VCore and Graphics – Multiphase buck controller, current sense resistors, and phase doubling.
- Page 12: Memory Power – +1.2V_VDDQ and VPP (2.5V for DDR4).
- Page 15-17: PCIe and Clocks – Differential pairs for SSD, WiFi, and clock generators (CK505).